Alta Pattern Set			15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	
SKIP																			
CCD:	U47 D9F		#NAME?																
System:	16 Bit		- step 0 must be final resting  state																
Pattern	M16HS1i																		
Date:	8/26/2009	Time (nS)	FIFO WR	SAM 2	SAM 1	CLAMP 16	CLAMP 12	CON 16	CON 12	INT 2	INT 1	RESET 2	RESET 1	S3	S2	S1	R	Stop	Row
	Mask		0	0	0	0	0	0	0	0	0	0	0	1	1	1	1	0	
	REFERENCE	0	0	0	0	0	0	0	0	0	0	1	1	0	1	1	0	0	1
		20	0	0	0	0	0	0	0	0	0	1	1	0	1	0	0	0	2
		40	0	0	0	0	0	0	0	0	0	1	1	0	1	0	1	0	3
		60	0	0	0	0	0	0	0	0	0	1	1	0	1	0	1	0	4
		80	0	0	0	1	0	0	0	0	0	1	1	0	1	0	0	0	5
		100	0	0	0	1	0	0	0	0	0	1	1	0	1	0	0	0	6
		120	0	0	0	1	0	0	0	0	0	1	1	0	1	0	0	0	7
		140	0	0	0	0	0	0	0	0	0	1	1	0	1	0	0	0	8
		160	0	0	0	0	0	0	0	0	1	1	1	0	1	0	0	0	9
		240	0	0	0	0	0	0	0	0	1	1	0	0	1	0	0	0	13
		260	0	0	0	0	0	0	0	0	1	1	0	1	1	0	0	0	14
	 	280	0	0	0	0	0	0	0	0	1	1	0	1	1	0	0	0	15
	 	300	0	0	0	0	0	0	0	0	1	1	0	1	1	0	0	0	16
	 	320	0	0	0	0	0	0	0	0	1	1	0	1	1	0	0	0	17
		340	0	0	0	0	0	0	0	0	1	1	0	1	0	0	0	0	18
		360	0	0	0	0	0	0	0	0	1	1	0	1	0	0	0	0	19
		380	0	0	0	0	0	0	0	0	1	1	0	1	0	0	0	0	20
		400	0	0	0	0	0	0	0	0	1	1	0	1	0	0	0	0	21
		420	0	0	0	0	0	0	0	0	1	1	0	1	0	1	0	0	22
		440	0	0	0	0	0	0	0	0	1	1	0	1	0	1	0	0	23
	 	460	0	0	0	0	0	0	0	0	1	1	0	1	0	1	0	0	24
	END	480	0	0	0	0	0	0	0	0	1	1	0	1	0	1	0	0	25
	BIN 1	500	0	0	0	0	0	0	0	0	0	1	0	1	0	1	0	0	26
	END	520	0	0	0	0	0	0	0	0	0	1	0	0	0	1	0	0	27
	SIGNAL	680	0	0	0	0	0	0	0	1	0	1	0	0	0	1	0	0	35
		700	0	0	0	0	0	0	0	1	0	0	0	0	0	1	0	0	36
		720	0	0	0	0	0	0	0	1	0	0	0	0	0	1	0	0	37
		980	0	0	0	0	0	0	0	1	0	0	0	0	0	1	0	0	50
		1000	0	0	0	0	0	0	0	1	0	0	0	0	0	1	0	0	51
	 	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	52
		20	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	1	53
	END	40	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	54