Alta Pattern Set			15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	

CCD:	U9000H		#NAME?																
System:	16 Bit		- step 0 must be final resting  state																
Pattern	K16HS8																		
Date:	2/15/2007	Time (nS)	FIFO WR	SAM 2	SAM 1	CLAMP 16	CLAMP 12	CON 16	CON 12	INT 2	INT 1	RESET 2	RESET 1	S3	S2	S1	R	Stop	Row
	Mask		0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	
	REFERENCE	0	0	0	0	0	0	0	0	0	0	1	1	0	1	0	0	0	1
		20	0	0	0	0	0	0	0	0	0	1	1	0	1	0	1	0	2
		40	0	0	0	0	0	0	0	0	0	1	1	0	1	0	1	0	3
		120	0	0	0	1	0	0	0	0	0	1	1	0	1	0	0	0	7
	END	480	0	0	0	1	0	0	0	0	0	1	1	0	1	0	0	0	25
	BIN 1	500	0	0	0	1	0	0	0	0	0	1	1	0	1	0	0	0	26
	END	520	0	0	0	0	0	0	0	0	0	1	1	0	0	1	0	0	27
	SIGNAL	540	0	0	0	0	0	0	0	0	0	1	1	0	0	1	0	0	28
		540	0	0	0	0	0	0	0	0	0	1	1	0	0	1	0	0	28
		540	0	0	0	0	0	0	0	0	0	1	1	0	0	1	0	0	28
		20	0	0	0	0	0	0	0	0	0	1	1	0	0	1	0	1	53
	END	40	0	0	0	0	0	0	0	0	0	1	1	0	0	1	0	0	54