Alta Pattern Set			15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	
																			
CCD:	77		#NAME?																
System:	16 Bit		- step 0 must be final resting  state																
Pattern	FF77S																		
Date:	11-May	Time (nS)	Latching	ADD/FIFO	RIGHT	FIFO		SAM 2L	SAM 1L	SAM 2R	SAM 1R	ADCLK	SW	S3	S2	S1	R	Stop	Row
	Mask		0	0	0	0	0	0	0	0	0	0	0	1	1	1	1	0	
	BIN1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	1	0	0	1
		10	0	0	0	0	0	0	0	0	0	0	0	0	1	1	0	0	2
		20	0	0	0	0	0	0	0	0	0	0	0	0	1	1	0	0	3
		30	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	13
		40	0	0	0	0	0	0	0	0	0	0	0	1	1	0	0	0	15
		50	0	0	0	0	0	0	0	0	0	0	0	1	1	0	0	0	17
		60	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	31
		70	0	0	0	0	0	0	0	0	0	0	0	1	0	0	1	0	33
		80	0	0	0	0	0	0	0	0	0	0	0	1	0	0	1	0	34
		90	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	61
		100	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	115
		110	0	0	0	0	0	0	0	0	0	0	0	1	0	1	0	0	116
		120	0	0	0	0	0	0	0	0	0	0	0	1	0	1	0	0	117
		130	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	127
		140	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	179
		150	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	180
		160	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	189
		170	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	1	191
	END	180	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	192