Alta Pattern Set			15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	
																			
CCD:	30-11		#NAME?																
System:	16 Bit		- step 0 must be final resting  state																
Pattern	FF30S																		
Date:	5/11/2012	Time (nS)	Latching	ADD/FIFO	RIGHT	FIFO		SAM 2L	SAM 1L	SAM 2R	SAM 1R	ADCLK	SW	S3	S2	S1	R	Stop	Row
	Mask		0	0	0	0	0	0	0	0	0	0	0	1	1	1	1	0	
	BIN 1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	1	1	0	1
		10	0	0	0	0	0	0	0	0	0	0	0	0	1	0	1	0	2
		20	0	0	0	0	0	0	0	0	0	0	0	0	1	0	1	0	3
		30	0	0	0	0	0	0	0	0	0	0	0	1	1	0	0	0	4
		40	0	0	0	0	0	0	0	0	0	0	0	1	1	0	0	0	5
	 	50	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	6
		60	0	0	0	0	0	0	0	0	0	0	0	1	0	1	0	0	7
		70	0	0	0	0	0	0	0	0	0	0	0	1	0	1	0	0	8
		80	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	9
		90	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	10
		100	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	11
		110	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	12
		120	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	1	13
	END	130	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	14