Alta Pattern Set			15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	
ROI																			
CCD:	3041		#NAME?																
System:	16 Bit		- step 0 must be final resting  state																
Pattern	F16Hs1		28 integration steps						sw										
Date:	0:00	Time (nS)	FIFO WR	SAM 2	SAM 1	CLAMP 16	CLAMP 12	CON 16	CON 12	INT 2	INT 1	RESET 2	RESET 1	S3	S2	S1	R	Stop	Row
	Mask		0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	0	
	REFERENCE	0	0	0	0	0	0	0	0	0	0	1	1	0	1	1	0	0	1
		20	0	0	0	0	0	0	1	0	0	1	1	1	0	1	1	0	2
		140	0	0	0	0	0	0	1	0	0	1	1	1	0	1	1	0	8
		160	0	0	0	0	0	0	1	0	0	1	1	1	0	1	1	0	9
		180	0	0	0	0	0	0	1	0	0	1	1	1	0	0	0	0	10
	 	320	0	0	0	1	0	0	1	0	0	1	1	1	0	0	0	0	17
		340	0	0	0	1	0	0	1	0	0	1	1	1	0	0	0	0	18
		360	0	0	0	0	0	0	1	0	1	1	1	1	0	0	0	0	19
		880	0	0	0	0	0	0	1	0	1	1	0	1	1	0	0	0	45
		900	0	0	0	0	0	0	1	0	1	1	0	1	1	0	0	0	46
	END	920	0	0	0	0	0	0	1	0	1	1	0	1	1	0	0	0	47
	BIN 1	940	0	0	0	0	0	0	0	0	0	1	0	0	1	0	0	0	48
	END	960	0	0	0	0	0	0	0	0	0	1	0	0	1	0	0	0	49
	SIGNAL	1060	0	0	0	0	0	0	0	0	0	1	0	0	1	0	0	0	54
		1080	0	0	0	0	0	0	0	1	0	1	0	0	1	0	0	0	55
		1340	0	0	0	0	0	0	0	1	0	0	0	0	1	1	0	0	68
		1360	0	0	0	0	0	0	0	1	0	0	0	0	1	1	0	0	69
		1620	0	0	0	0	0	0	0	1	0	0	0	0	0	1	0	0	82
		1640	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	83
		1720	0	0	0	0	0	1	0	0	0	0	0	0	0	1	0	1	87
	END	1740	0	0	0	0	0	1	0	0	0	0	0	0	0	1	0	0	88