Alta Pattern Set 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CCD: 7899 #NAME? System: 12 Bit - step 0 must be final resting state Pattern clamp Date: 3/9/2005 Time (nS) FIFO WR SAM 2 SAM 1 CLAMP 16 CLAMP 12 CON 16 CON 12 INT 2 INT 1 RESET 2 RESET 1 S3 S2 S1 R Stop Row Mask 0 1 1 0 1 0 0 0 0 0 0 1 1 1 1 0 BIN 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 0 1 20 0 0 0 0 1 0 0 0 0 0 0 1 1 0 1 0 2 40 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 3 60 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 4 80 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 5 100 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 6 120 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 7 140 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 8 160 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 9 180 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 10 200 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 11 END 220 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 12 240 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13 260 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 280 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 300 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 320 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 340 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18 360 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19 380 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 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